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| UL (R) LSI/CSI LS7082N1 (631) 271-0400 FAX (631) 271-0405 April 2009 PIN ASSIGNMENT - TOP VIEW V DD (+V ) INDX RBIAS V SS (-V ) A NC NC 14 13 12 A3800 LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 FEATURES: * x1, x2 and x4 mode selection * Up to 16MHz output clock frequency * INDEX input and output * UP/DOWN indicator output * Programmable output clock pulse width * On-chip filtering of inputs for optical or magnetic encoder applications. * TTL and CMOS compatible I/Os * +3V to +12V operation (VDD - VSS) * LS7082N1 (DIP); LS7082N1-S (SOIC ) - See Figure 1 QUADRATURE CLOCK CONVERTER 1 2 3 LSI INDX UPCK DNCK UP/DN x4/x1 B x2 LS7082N1 4 5 6 7 11 10 9 8 DESCRIPTION: The LS7082N1 is a CMOS quadrature clock converter. Quadrature clocks derived from optical or magnetic encoders, when applied to the A and B Inputs of the LS7082N1, are converted to strings of Up Clocks and Down Clocks. Pulses derived from the Index Track of an encoder, when applied to the INDX input, produce absolute position reference pulses which are synchronized to the Up Clocks and Down Clocks. These outputs can be interfaced directly with standard Up/Down counters for direction and position sensing of the encoder. INPUT/OUTPUT DESCRIPTION: VDD (Pin 1) Supply Voltage positive terminal. INDX (Pin 2) Encoder Index pulses are applied to this input. RBIAS (Pin 3) Input for external component connection. A resistor connected between this input and VSS adjusts the output clock pulse width (Tow). For proper operation, the output clock pulse width must be less than or equal to the A, B pulse separation (TOW TPS). VSS (Pin 4) Supply Voltage negative terminal. A (Pin 5) Quadrature Clock Input A. This input has a filter circuit to validate input logic level and eliminate encoder dither. x2 (Pin 8) A low level applied to this input selects x2 mode of operation. See Table 1 for Mode Selection Truth Table and Figure 2 for Input/Output timing relationship. B (Pin 9) Quadrature Clock Input B. This input has a filter circuit identical to input A. 7082N1-043009-1 FIGURE 1 TABLE 1. MODE SELECTION TRUTH TABLE x2 Input 0 1 1 x4/x1 Input 0 or 1 0 1 MODE x2 x1 x4 x4/x1 (Pin 10) This input selects between x1 and x4 modes of operation. See Table 1 for Mode Selection Truth Table and Figure 2 for Input/Output timing relationship. UP/DN (Pin 11) The count direction at any instant is indicated at this output. An UP count direction is indicated by a high, and a DOWN count direction is indicated by a low (See Figure 2). DNCK (Pin 12) This DOWN Clock output consists of low-going pulses generated when A input lags the B input (See Figure 2). UPCK (Pin 13) This UP Clock output consists of low-going pulses generated when A input leads the B input (See Figure 2). INDX (Pin 14) This output consists of low-going pulses generated by a positive clock transition at the A input when INDX input is high and B input is low and a negative clock transition at the B input when INDX input is high and A input is high. (See Figure 2). NOTE: All unused input pins must be tied to VDD or VSS. ABSOLUTE MAXIMUM RATINGS: PARAMETER SYMBOL DC Supply Voltage VDD - VSS Voltage at any input VIN Operating temperature TA Storage temperature TSTG DC ELECTRICAL CHARACTERISTICS: (All voltages referenced to VSS, TA = 0C to 85C.) PARAMETER Supply voltage Supply current x4/x1 x2, INDX Logic Low A, B Logic Low x4/x1 x2, INDX Logic High A, B Logic High SYMBOL VDD IDD VIL VIL VIL VIH VIH VIH VALUE 16.0 VSS - 0.3 to VDD + 0.3 0 to +85 -55 to +150 UNITS V V C C MIN 3.0 VDD - 0.5 0.7VDD 2.0 3.0 6.6 1.3 1.9 2.9 0.83 1.1 1.6 MAX 12.0 20 0.5 0.3VDD 0.7 1.0 2.8 - UNITS V A V V V V V V V V V V mA mA mA mA mA mA CONDITION VDD = 12V, All input frequencies = 0Hz RBIAS = 2M VDD = 3V VDD = 5V VDD = 12V VDD = 3V VDD = 5V VDD = 12V VDD = 3V VDD = 5V VDD = 12V VDD = 3V VDD = 5V VDD = 12V ALL OUTPUTS: Sink Current VOL = 0.4V Source Current VOH = VDD - 0.5V TRANSIENT CHARACTERISTICS: (TA = 0C to 70C) PARAMETER A, B inputs: Validation Delay A, B inputs: Pulse Width A to B or B to A Phase Delay A, B frequency Input to Output Delay IOL IOH SYMBOL TvD MIN TVD + TOW TOW - MAX 250 170 71 Infinite Infinite 1 2TPW 280 220 120 UNITS ns ns ns ns ns Hz ns ns ns CONDITION VDD = 3V VDD = 5V VDD = 12V VDD = 3V VDD = 5V VDD = 12V Includes input validation delay See Fig. 4 & 5 TPW TPS fA, B TDS Output Clock Pulse Width TOW 50 - ns 7082N1-043009-2 TPW A B INDX UPCK (x1 ) DNCK (x1 ) UPCK (x2 ) DNCK (x2 ) UPCK (x4 ) DNCK (x4 ) INDX UP/DN TDS TPS TDS Tow FIGURE 2. LS7082N1 INPUT/OUTPUT TIMING DIAGRAM RBIAS 3 CURRENT MIRROR 14 INDX A 5 FILTER DUAL ONE-SHOT CLOCK AND DIRECTION DECODE x2 CLOCK MUX 11 UP/DN 13 B9 FILTER DUAL ONE-SHOT 12 INDX 2 x4/x1 10 x2 VDD V SS 8 1 +V -V 4 FIGURE 3. LS7082N1 BLOCK DIAGRAM 7082N1-043009-3 NOTE : Vertical axis is output clock pulse width, Tow, ns VDD = 3V 1500 1250 1000 VDD = 5V NOTE: Vertical axis is output clock pulse width, Tow, s 30 25 20 VDD = 3V VDD = 5V VDD = 9V VDD = 12V V DD = 9V 750 15 VDD = 12V 500 10 250 5 100 200 300 400 500 2 4 6 8 BIAS , 10 12 Figure 4. Tow vs R BIAS , k Figure 5. Tow vs R M +V 8 x2 A CLOCK ENCODER B CLOCK INDEX 5 9 2 A B 10 x4/x1 1 V DD UPCK 13 12 14 5 4 14 UPCK DNCK RESET V SS RBIAS 3 V SS 4 8 +V 16 V DD LS7082N1 DNCK INDX 40193 INDX RB FIGURE 6. A TYPICAL APPLICATION in x4 MODE NOTE: When driving a counter that requires CLK and Direction input, the UPCK and DNCK must be externally "Ored" together to generate one clock, CLK. CLK can be applied directly to the Clock input of counters that advance on the positive edge of the clock. If the counter advances on the negative edge of the clock, an inverter must be added between CLK and the Clock input of the counter. 7082N1-043009-4 The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. |
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